This invention relates to an apparatus and a process for the rapid processing of segmented data.
In prior art data processing systems segmenting of the memories, the central processor memory, as well as the auxiliary memories, has been implemented by assigning an identification number to each memory segment and by storing the characteristics of each segment (address, length, access rights, etc.) termed "segment descriptor" in a particular register. The set of these descriptors constitutes a general table of segment descriptors. This arrangement has the advantage of simplifying the task of the programmer for whom the central processor memory and the auxiliary memories then form a unit which may be considered as a single memory.
In a system organized in this manner, when the address calculating mechanism furnishes the identification number of a segment, the corresponding descriptor must be located in the general table in order to provide for controlling the access rights, verifying if the length of the segment is sufficient for the capacity demanded by the program, and locating such segment by the address held in the descriptor.
When the capacity of the memory unit is very large, the number of segments and, therefore, of descriptors is very large. In such instance the selection of a descriptor from the general table is performed by an approach termed "hierarchizing", which increases considerably the time for locating a descriptor. The preformance of such systems is therefore limited.
Accordingly, it is the object of this invention to reduce the time for selecting segment descriptors in a data processing system having segmented memories.
Another object of this invention is to increase the preformance of a data processing system having segmented memories.